1. Field of the Invention
The present invention relates to a dynamic memory integrated circuit wherein a reduced leakage of stored charge from a memory cell is obtained.
2. Description of the Prior Art
Dynamic random access memories (DRAMs) store information by placing a desired voltage on a storage capacitor, thereby charging or discharging the capacitor correspondingly. In the case of binary information, the stored voltage is nominally at one of two levels, referred to as the "1" and the "0" levels. In present generation designs, the 1 level is typically about 3.5 to 5 volts with respect to ground (VSS), and the 0 level is about 0 volts. It is also possible to store more than two voltage levels in a dynamic memory; see, for example, "A 16-Levels/Cell Dynamic Memory", M. Aoki et al, 1985 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pages 246-247 (1985). In current designs, the charge is transferred into or out of the storage capacitor by means of an access transistor. The access transistor is typically a field effect transistor, wherein a voltage placed on the gate controls the conduction of charge through the channel between the source and drain electrodes.
Referring to FIG. 1, a representative array of DRAM cells is illustrated. In many designs, a multiplicity of arrays are used on a given integrated circuit chip, or on a wafer in the case of wafer scale integration. Each of the arrays is then often referred to as a "sub-array". An array comprises a multiplicity of memory cells arranged in row and columns. Each cell comprises an information storage capacitor (e.g., 10) and an associated access transistor (e.g., M11). The gate of the access transistor is connected to a row conductor (e.g., R1), and a source/drain electrode to a column conductor (e.g., C1). The other source/drain electrode of the access transistor is connected to one plate of the storage capacitor. Note that which of the transistor controlled electrodes serves as the source and which as the drain depends upon the voltage present on the storage capacitor and the column conductor at any given time.
A desired row of memory cells is selected for a read or write operation when the row decoder places the appropriate access voltage on a row conductor. This voltage allows the access transistors in the selected row to conduct, thereby allowing the column conductors to communicate with the storage capacitors along the selected row. Normally, a single row is selected at any one time in a given array, although a reference row may also be selected to access a dummy cell in the given array. A corresponding row (i.e., one specified by the same row address bits) may simultaneously be selected in another sub-array. Then, a column is selected by the column decoder for performing an input (write) or output (read) operation from the selected cell during the active portion of a memory cycle.
Dynamic memories by their nature require periodic refreshing of the information stored in the cells. This is due to leakage of charge stored in the capacitor. Such leakage may occur from a capacitor plate to the substrate, and also through the access transistor, among other ways. The latter phenomenon, referred to as "sub-threshold leakage" occurs because the channel of the field effect access transistor can never be rendered entirely non-conducting by the gate voltage. Therefore, a refresh voltage, usually supplied by the sense amplifier, is applied to the cell periodically. At present, the periodic refresh occurs about every 4 to 9 milliseconds in most designs. A refresh is also provided at the end of each memory cycle in typical designs.
Furthermore, some modes of memory access, such as "page mode" and "fast column", allow cells to be accessed at a number of desired locations along a selected row by merely performing repeated column access operations; see, for example, "A 1Mb CMOS DRAM", H. C. Kirsch et al, 1985 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 256-257. In these access modes the row decoding process need be accomplished only once, as long as the desired cells are located on the selected row. Hence, the active portion of the memory cycle may be very long in duration. These access modes place a premium on the length of time the cells may be accessed without a refresh, since a refresh may interrupt a high data rate read operation, and also may necessitate that the row decoding operation be performed again. However, the time interval before a required refresh during page mode or fast column or during long active cycles may be limited, because of leakage through the access transistor. Furthermore, in these modes the information hold time is less than in other access modes wherein the column conductors are precharged between cell accesses. This is because the voltage level of a precharged column conductor typically is such as to reduce the sub-threshold leakage through the access transistors connected thereto. Hence, the use of page mode, fast column mode, long active cycles, etc. make an increase in memory hold time desirable.
In addition, there is a trend toward lower operating voltages (i.e., less than 5 volts) for dynamic memories, due to the reduction in transistor sizes. This in turn makes a reduction in the access transistor threshold voltage (Vth) desirable for circuit reasons. However, the leakage current is a very non-linear function of threshold voltage, so that reduced thresholds allow increased leakage currents. Hence, it is desirable to obtain a dynamic random access memory that compensates for increased sub-threshold leakage.